工作地区:Shenzhen -Futian 工作性质:性别要求:No limit薪资:Interview工作经验:More than three years年龄要求:
Proficient in Verilog HDL, familiar with related EDA tools, familiar with processes such as DC, PT, DFT, ATPG, etc., with certain debugging abilities;
Having a solid foundation in digital circuit design, familiar with the design process, and possessing excellent learning, analysis, and innovation abilities;
Having been exposed to Low Power design technology, I have a certain understanding of Low Power design;
Have good communication skills in both Chinese and English (including document writing);
Having good interpersonal communication skills, initiative, and teamwork spirit;
Experience in IC product design mentioned above is preferred.